1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently handling translation look-aside buffer (TLB) misses.
2. Description of the Relevant Art
Modern microprocessors typically include two or three levels of cache hierarchy for a processor core or for multiple cores. Later levels in the hierarchy of the system memory may include access via a memory controller to dynamic random-access memory (DRAM), dual in-line memory modules (dimms), and a hard disk. Data from recently accessed external memory locations are stored within the multiple levels of caches. When the data is requested again, the data may be retrieved from the caches rather than from external memory.
The processor utilizes linear addresses when processing the accessed data. The linear addresses may also be referred to as virtual addresses. A virtual address space for the data stored in system memory and used by a software process may be divided into pages of a prefixed size. The virtual pages may be mapped to frames of physical memory. Mappings of virtual addresses to physical addresses may keep track of where virtual pages are loaded in the physical memory. These mappings are stored in a page table and this page table is stored in memory. A translation look-aside buffer (TLB) stores a subset of the page table.
The TLB may reside between a processor and a given level of the cache hierarchy. Alternatively, a TLB may reside between two levels of the system memory hierarchy. In use, the TLB is accessed with a linear address of a given memory access request to determine whether the TLB contains an associated physical address for a memory location holding requested data. If a mapping is not found within the TLB, then the address translation is performed by a lookup of the page table. This lookup process is referred to as a page table walk. The page table walk includes reading the contents of multiple memory locations and using them to compute the associated physical address. After the completed page table walk, the physical address is used to complete an associated memory access request and the linear address to physical address mapping is entered into the TLB.
The page table walk utilizes an appreciable amount of execution time, multiple accesses of the system memory and associated memory resources such as buses and ports. The page table walk may interfere with other memory access operations such as load and store operations that hit in the TLB. By acquiring resources from the memory system, the page table walk is able to reduce the performance of the other load and store operations. Speculative page table walks correspond to speculative memory access requests that missed in the TLB. The result of the speculative page table walk may be flushed at a later time, rather than committed and later retired. However, these speculative page table walks acquire memory system resources and further interfere with memory access requests that hit in the TLB.
In view of the above, efficient methods and mechanisms for efficiently handling translation look-aside buffer (TLB) misses are desired.